`timescale 1ns / 1ps
//   _a
// |f |b
//  -g
// |e |c
//  -d
// doesn't shows the dot
module decoder_3_seg(
    input [3:0] binary,
	input dot_ctrl,
    output reg [7:0] seg_ctrl
    );
    
    always @(binary, dot_ctrl) begin
        case (binary)
            4'b0000: seg_ctrl <= {7'b1111110, dot_ctrl};
            4'b0001: seg_ctrl <= {7'b0110000, dot_ctrl};
			4'b0010: seg_ctrl <= {7'b1101101, dot_ctrl};
            4'b0011: seg_ctrl <= {7'b1111001, dot_ctrl};
			4'b0100: seg_ctrl <= {7'b0110011, dot_ctrl};
            4'b0101: seg_ctrl <= {7'b1011011, dot_ctrl};
			4'b0110: seg_ctrl <= {7'b1011111, dot_ctrl};
            4'b0111: seg_ctrl <= {7'b1110000, dot_ctrl};
			4'b1000: seg_ctrl <= {7'b1111111, dot_ctrl};
            4'b1001: seg_ctrl <= {7'b1111011, dot_ctrl};
			4'b1010: seg_ctrl <= {7'b1110111, dot_ctrl};
            4'b1011: seg_ctrl <= {7'b0011111, dot_ctrl};
			4'b1100: seg_ctrl <= {7'b0001101, dot_ctrl};
            4'b1101: seg_ctrl <= {7'b0111101, dot_ctrl};
			4'b1110: seg_ctrl <= {7'b1001111, dot_ctrl};
            4'b1111: seg_ctrl <= {7'b1000111, dot_ctrl};
			default: seg_ctrl <= {7'b0000000, dot_ctrl};
        endcase
    end
endmodule